Figure 7.17: An AND-OR gate used as a ``ones catching'' latch and its timing diagram.
When the control input C is false, the output Q follows the input D, but when the control input goes true, the output latches true as soon as D goes true and then stays there independent of further changes in D.
One of the most useful latches is known as the transparent latch or D-type latch. The transparent latch is like the ones-catching latch but the input D is frozen when the latch is disabled. The operation of this latch is the same as that of the statically triggered D flip-flop discussed below.
RS and Flip-Flops
The RS flip-flop (RSFF) is the result of cross-connecting two NOR gates as shown in figure 7.18. The RS inputs are referred to as active ones.Figure 7.18: The RS flip-flop constructed from NOR gates, and its circuit symbol and truth table.
The ideal flip-flop has only two rest states, set and reset, defined by and , respectively.
A very similar flip-flop can be constructed using two NAND gates as shown in figure 7.19. The inputs are now active zeros.
Figure 7.19: The flip-flop constructed from NAND gates, and its circuit symbol and truth table.
These FFs are often referred to as the set/reset type and are un-clocked.
Clocked Flip-Flops
A clocked flip-flop has an additional input that allows output state changes to be synchronized to a clock pulse.D Flip-Flop
The D flip-flop avoids the undefined states in the RSFF truth table by reducing the number of input options (figure 7.21).
Figure 7.21: Statically triggered D flip-flop (transparent latch) mechanized with clocked RS, and the schematic symbol and its truth table.
The statically clocked DFF is also known as a transparent latch.
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